This invention relates to programmable logic array (PLA) integrated circuits, and more particularly to a PLA integrated circuit that combines low power circuitry with high performance interconnect architecture.
As shown by commonly-assigned U.S. Pat. No. 4,871,930 ("Wong"), which is hereby incorporated by reference in its entirety, and the references cited therein, programmable logic devices (PLD's) are well known integrated circuits. As described in Wong, a major obstacle in increasing the logic density in previously known PLDs was the size of the single global interconnection array which increased as the square of the number of output functions. This obstacle was overcome to a large extent by the use of a programmable interconnect array ("PIA") disclosed in Wong. In a PLD using a PIA, a single global interconnection array using erasable programmable read-only memory ("EPROM") cells was used to route signals to and from logic array blocks ("LABs") which contained logic elements, logic modules, and a local interconnection array.
The architecture using PIAs and LABs disclosed in Wong produced a generation of successful PLDs available commercially from Altera Corporation of San Jose, Calif. Yet, to meet ever increasing technological demands, PLDs have been constantly increasing in both size and complexity. In particular, to achieve higher logic density, more logic elements have been incorporated into PLDs and this has necessitated increasing the size of the PIA. However, a significant amount of the power used in PLDs is consumed in the programmable elements of the PIA, and a speed limitation is capacitive loading in the programmable elements of the PIA. Increasing the size of the PIA, therefore, leads undesirably to higher power consumption and reduction in speed.
An enhancement to the PIA was disclosed in a commonly-assigned U.S. patent application Ser. No. 07/691,640, filed Apr. 25, 1991, now U.S. Pat. No. 5,241,224, that successfully addressed the above problems associated with increased chip density. It was realized that, as the complexity of PLDs increases, the increase in the number of programmable elements in the PIA is responsible for a significant increase in the amount of the power consumed, and is responsible for a significant decrease in the speed due to the capacitive loading of EPROM cells. Furthermore, it was observed that only a small fraction of the total number of EPROM cells in the PIA is used, so that most of the increased capacitive loading and power consumption is unnecessary.
Accordingly, in the enhanced PIA architecture, the programmable elements and thus their associated power consumption and capacitive loading were eliminated by an alternative global interconnect array (GIA) architecture. In the GIA, selected global conductors are connected to the inputs of a group of multiplexers in a predetermined pattern, and the outputs of the multiplexers are connected to the inputs of logic modules in the LABs. Programmability through the use of a global EPROM in the PIA of the prior PLDs is replaced by programmability of the multiplexers connected to the GIA. The multiplexers are controlled by an array of programmable architecture bits so that the signals on selected global conductors can be routed to the inputs of selected logic modules.
Replacement of the PIA with GIA allowed for higher logic density than previously possible. For example, a preferred embodiment of the GIA architecture disclosed in the above-mentioned co-pending patent application Ser. No. 691,640 provides up to twice the density of the EPM5128, available commercially from Altera Corporation of San Jose, Calif. That embodiment comprises sixteen LABs interconnected with a high speed GIA, with each LAB containing sixteen logic modules that share a programmable local EPROM array.
While significant improvements in chip density, power consumption and speed are realized by the replacement of the PIA with the GIA, the DC power consumed by the EPROM based product term logic places an upper limit on the practical density achievable. Even for smaller numbers of product terms, the presence of DC power consumption on a chip can limit the range of its applicability.
There is therefore a need for an improved programmable logic device that can achieve higher logic densities at lower levels of power consumption.